Functional Test Pattern Generation for Maximizing Temperature in 2D and 3D Integrated Circuits PDF Download

Author: Sudarshan Srinivasan
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 84

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Book Description
Localized heating leads to generation of thermal Hotspots that affect performance and reliability of an Integrated Circuit(IC). Functional workloads determine the locations and temperature of hotspots on a die. Programs are classified into phases based on program execution profile. During a phase, spatial power dissipation pattern of an application remains unchanged. In this thesis, we present a systematic approach for developing a synthetic workload from a functional workload to create worst case temperature of a target hotspot in 2D and 3D IC. These synthetic workload are designed to create thermal stress patterns, which would help in characterizing the thermal characteristics of micro architecture to worst case temperature transient which is an important problem in Industry. Our approach is based on the observation that, worst case temperature at a particular location in 2 D IC is determined not only by the current activity in that region, but also by the past activities in the surrounding regions. Therefore, if the surrounding areas were "pre-heated" with a different workload, then the target region may become hotter due to slower rate of lateral heat dissipation Similarly in case of 3D IC, the workload applied to each of the dies in 3D IC keeps on changing continuously, thus the hotspot could be found in any of the stacked layers. Thus the creation of localized hotspot at a particular location in a stacked 3D IC layer depends not only on the present activity at that location but also on the previous activity in the surrounding region and also on the activity of layers below it. Accordingly, (i) we develop a wavelet-based canonical spatio-temporal heat dissipation model for program traces, and use (ii) a novel Integer Linear Programming (ILP) formulation to rearrange program phases to generate target worst case hotspot temperature in 2D and 3D IC. We apply this formulation to target another well-known problem of (iii) maximizing temperature between a pair of co-ordinates in an IC. Experimental results show that by taking the spatio-temporal effect into account and with dynamic phase change behavior, we could raise temperature of a hotspot higher than what is possible otherwise. ICs are often tested at worst-case system operating conditions to assure that, all ICs shipped will function properly in the end system. Thus hotspot temperature maximization is an important in design verification and testing.