Fabricate Indium-Antimonide Two-Dimensional Charge Injection Device Array PDF Download
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Author: C. -Y. Wei
Publisher:
ISBN:
Category :
Languages : en
Pages : 29
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Book Description
The objective of this program was to fabricate 16x64 two-dimensional InSb CID arrays using the process sequence developed by GE CR & D under contract N00173-80-C-0281. This process sequences does not involve a thick-thin cut back of the pixel gate oxide and therefore produces an essentially planar structure. InSb CID focal plane arrays with 16x64 elements have been fabricated and various 2-D CID modes demonstrated on test structures incorporated on the chips. Low threshold voltages, low density of states in the interfaces and in the gate oxides and dual-gate coupling between row and column gates of less than one volt have led to the demonstration of practical ideal mode behavior. (Author).
Author: C. -Y. Wei
Publisher:
ISBN:
Category :
Languages : en
Pages : 29
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Book Description
The objective of this program was to fabricate 16x64 two-dimensional InSb CID arrays using the process sequence developed by GE CR & D under contract N00173-80-C-0281. This process sequences does not involve a thick-thin cut back of the pixel gate oxide and therefore produces an essentially planar structure. InSb CID focal plane arrays with 16x64 elements have been fabricated and various 2-D CID modes demonstrated on test structures incorporated on the chips. Low threshold voltages, low density of states in the interfaces and in the gate oxides and dual-gate coupling between row and column gates of less than one volt have led to the demonstration of practical ideal mode behavior. (Author).
Author: C. -Y. Wei
Publisher:
ISBN:
Category :
Languages : en
Pages : 31
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Book Description
A 'non-etch-back' fabrication technique has been developed for an InSb two-dimensional infrared sensitive charge injection device. This report summarizes the first phase of a two phase program and describes the fabrication technique and test results on a set of experimental configurations. The performance objectives relating to lag, well capacity, and charge transfer have been met. The second phase of this program has been initiated which is to fabricate the 16 x 64 2-D CID arrays. (Author).
Author: C. -Y. Wei
Publisher:
ISBN:
Category :
Languages : en
Pages : 52
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Book Description
Indium antimonide CID infrared detector arrays have been fabricated by a planar, or non-etch back, process and their performance has been determined. Four design variations were processed using this planar structure. The best performance at an injection voltage of 2 V and an integration time of 55 microsec gave a noise level of 1000 carriers for the array alone after correcting for the preamplifier noise of 1450 carriers. The saturation charge was 2.3 x 10 to the 7th power carriers at 2 V, the lag was 6%, the cross talk was 3%, and the performance efficiency was about 65%. Dark currents were generally less than 3 nA and there was no rapid increase in dark current for injection voltages at least as large as 2.4 volts implying that larger injection voltages and well capacities are possible. The array performance demonstrated in this program fully meets the specifications of the Navy IRST program.
Author:
Publisher:
ISBN:
Category : Aeronautics
Languages : en
Pages : 1572
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Book Description
Author: J. C. Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 115
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Book Description
Two-dimensional 16x24 InSb CID area arrays have been designed and successfully fabricated via a multilayer MIS processing technique. The operation of these arrays in a staring mode has been demonstrated by displaying real time raster-scanned IR images on an X-Y CRT monitor. The raw video image displays were as sharp as the actual objects, being clearly recognizable with no sign of blooming and, therefore, excellent operating characteristic. Theoretical analysis showed that at low sample rates, a background limited performance (BLIP) can be obtained at background photon flux levels of as low as mid-10 to the 12th power photons/sec-sq cm. The dominant noise source, in this case, is the integrated dark current shot noise. For operation at high sample rates, however, the bandwidth-dependent noise sources limit the array performance and, thus, BLIP occurs at higher background levels. The analysis has been confirmed by measured data on line arrays, resulting in good agreement between the theoretical curve and the experimental data. (Author).
Author: J. C. Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 95
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Book Description
The successful development of InSb charge injection device (CID) arrays has been made possible by the recent success of our InSb MIS technology, which is now capable of producing two-dimensional InSb CID arrays. This Final Report describes the development of 1 x 16 two-dimensional InSb CID arrays. The InSb wafer material preparation is described in Section 2. The improved interface state densities of InSb MIS structures are presented in Section 3. The sensitivity measurements of linear arrays is discussed and the results are presented in Section 4. In Section 5, we describe the array fabrication process; silicon shift register scanners are discussed in Section 6. The array evaluation measurements are discussed in Section 7 and finally, conclusions and recommendations are presented in Section 8.
Author: Technology Reports Centre (Great Britain)
Publisher:
ISBN:
Category :
Languages : en
Pages : 612
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Book Description
Author: Aeronautical Research Council (Great Britain)
Publisher:
ISBN: 9780114709266
Category : Airplanes
Languages : en
Pages : 1212
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Book Description
Author: Antoni Rogalski
Publisher: SPIE-International Society for Optical Engineering
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 672
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Book Description
Author: Michael S. Schippers
Publisher:
ISBN:
Category : Imaging systems
Languages : en
Pages : 778
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Book Description
"Charge-injection devices (CID's) have been around almost as long as charge-coupled devices (CCD's), yet have generally been overlooked for solid state imaging applications due to their slower operating speeds. However, CID arrays offer advantages over CCD based arrays for certain applications where spectral response and/or X-Y addressing are required. In order to fabricate CID based imaging arrays, a single level poly CMOS (p-well) process has been modified into a double level poly CMOS (p-well) process that will allow fabrication of both imaging structures and drive circuitry. These modifications are optimized for CID based structures, yet will also allow working CCD based arrays to be fabricated with this process. Measurements obtained from processed wafers were compared to values obtained using SUPREM IV simulation software from Technology Modeling Associates Inc. and after analysis, further recommendations were made to improve the process."--Abstract.
