Author: Rengarajan Ragavan
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
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Book Description
Dynamic voltage scaling (DVS) technique is primarily used in digital design to enhance the energy efficiency by reducing the supply voltage of the design. However reduction in Vdd augments the impact of variability and timing errors in sub-nanometer designs. The main objective of this work is to handle timing errors, and to formulate a framework to estimate energy consumption of error resilient applications in the context of near-threshold regime (NTR). In this thesis, Dynamic Speculation based error detection and correction is explored in the context of adaptive voltage and clock overscaling. Apart from error detection and correction, some errors can also be tolerated or, in other words, circuits can be pushed beyond their limits to compute incorrectly to achieve higher energy efficiency. The proposed error detection and correction method achieves 71% overclocking with 2% additional hardware cost. This work involves extensive study of design at gate level to understand the behaviour of gates under overscaling of supply voltage, bias voltage and clock frequency (collectively called as operating triads). A bottom-up approach is taken: by studying trends of energy vs. error of basic arithmetic operators at transistor level. Based on the profiling of arithmetic operators, a tool flow is formulated to estimate energy and error metrics for different operating triads. We achieve maximum energy efficiency of 89% for arithmetic operators like 8-bit and 16-bit adders at the cost of 20% faulty bits by operating in NTR. A statistical model is developed for the arithmetic operators to represent the behaviour of the operators for different variability impacts. This model is used for approximate computing of error resilient applications that can tolerate acceptable margin of errors. This method is further explored for execution unit of a VLIW processor. The proposed framework provides quick estimation of energy and error metrics of a benchmark programs by simple compilation in a C compiler. In the proposed energy estimation framework, characterization of arithmetic operators is done at transistor level, and the energy estimation is done at functional level. This hybrid approach makes energy estimation faster and accurate for different operating triads. The proposed framework estimates energy for different benchmark programs with 98% accuracy compared to SPICE simulation.
Author: Sanghamitra Roy
Publisher: MDPI
ISBN: 3036507205
Category : Technology & Engineering
Languages : en
Pages : 120
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Book Description
Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing.
Author: Robert Stephen Pawlowski
Publisher:
ISBN:
Category : Digital electronics
Languages : en
Pages : 128
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Book Description
Scaling the supply voltage into the sub/near-threshold domain is one of the most effective methods for improving the energy efficiency of next-generation electronic microsystems. Unfortunately, the relationship between low-voltage operation and radiation-induced soft error rate is not widely known, as little research has been previously performed and reported for soft-error susceptibility of on-chip memory and logic at very low supply voltages. This information is critical for low-voltage circuit designers, as many applications that would benefit from the energy efficiency of sub/near-threshold also require high reliability. This work first details the design and implementation of a portable soft error reference platform, specifically targeting very low-voltage operation. The circuit-level details of a TSMC 65nm test-chip design are given, along with an analysis of data from experiments performed at Los Alamos Neutron Science Center (LANSCE) and the OSU Radiation Center. Once this soft-error rate is known, error resiliency techniques must be utilized for increased processor reliability. The design and implementation of an error-resilient, near-threshold SIMD processor in an IBM 45nm SOI process will also be covered. This prototype demonstrates both increased reliability and improved throughput over a conventional SIMD pipeline while operating in near-threshold.
Author: Svetlana N. Yanushkevich
Publisher: Springer Nature
ISBN: 3031798554
Category : Technology & Engineering
Languages : en
Pages : 132
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Book Description
Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work
Author: Massimo Alioto
Publisher: Springer
ISBN: 3319514822
Category : Technology & Engineering
Languages : en
Pages : 527
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Book Description
This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. After providing a system perspective on IoT nodes, this book focuses on state-of-the-art design techniques for IoT applications, encompassing the fundamental sub-systems encountered in Systems on Chip for IoT: ultra-low power digital architectures and circuits low- and zero-leakage memories (including emerging technologies) circuits for hardware security and authentication System on Chip design methodologies on-chip power management and energy harvesting ultra-low power analog interfaces and analog-digital conversion short-range radios miniaturized battery technologies packaging and assembly of IoT integrated systems (on silicon and non-silicon substrates). As a common thread, all chapters conclude with a prospective view on the foreseeable evolution of the related technologies for IoT. The concepts developed throughout the book are exemplified by two IoT node system demonstrations from industry. The unique balance between breadth and depth of this book: enables expert readers quickly to develop an understanding of the specific challenges and state-of-the-art solutions for IoT, as well as their evolution in the foreseeable future provides non-experts with a comprehensive introduction to integrated circuit design for IoT, and serves as an excellent starting point for further learning, thanks to the broad coverage of topics and selected references makes it very well suited for practicing engineers and scientists working in the hardware and chip design for IoT, and as textbook for senior undergraduate, graduate and postgraduate students ( familiar with analog and digital circuits).
Author: Sherief Reda
Publisher: Springer
ISBN: 3319993224
Category : Technology & Engineering
Languages : en
Pages : 479
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Book Description
This book provides readers with a comprehensive, state-of-the-art overview of approximate computing, enabling the design trade-off of accuracy for achieving better power/performance efficiencies, through the simplification of underlying computing resources. The authors describe in detail various efforts to generate approximate hardware systems, while still providing an overview of support techniques at other computing layers. The book is organized by techniques for various hardware components, from basic building blocks to general circuits and systems.
Author: Jörg Henkel
Publisher: Springer Nature
ISBN: 303052017X
Category : Technology & Engineering
Languages : en
Pages : 606
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Book Description
This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems.
Author: Azzedine Boukerche
Publisher: CRC Press
ISBN: 1420035096
Category : Computers
Languages : en
Pages : 1042
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Book Description
The Handbook of Algorithms for Wireless Networking and Mobile Computing focuses on several aspects of mobile computing, particularly algorithmic methods and distributed computing with mobile communications capability. It provides the topics that are crucial for building the foundation for the design and construction of future generations of mobile and wireless networks, including cellular, wireless ad hoc, sensor, and ubiquitous networks. Following an analysis of fundamental algorithms and protocols, the book offers a basic overview of wireless technologies and networks. Other topics include issues related to mobility, aspects of QoS provisioning in wireless networks, future applications, and much more.
Author: Prabhat
Publisher: CRC Press
ISBN: 1466582359
Category : Computers
Languages : en
Pages : 436
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Book Description
Gain Critical Insight into the Parallel I/O EcosystemParallel I/O is an integral component of modern high performance computing (HPC), especially in storing and processing very large datasets to facilitate scientific discovery. Revealing the state of the art in this field, High Performance Parallel I/O draws on insights from leading practitioners,
Author: Tomasz Wojcicki
Publisher: CRC Press
ISBN: 1351831437
Category : Technology & Engineering
Languages : en
Pages : 490
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Book Description
Recently the world celebrated the 60th anniversary of the invention of the first transistor. The first integrated circuit (IC) was built a decade later, with the first microprocessor designed in the early 1970s. Today, ICs are a part of nearly every aspect of our daily lives. They help us live longer and more comfortably, and do more, faster. All this is possible because of the relentless search for new materials, circuit designs, and ideas happening on a daily basis at industrial and academic institutions around the globe. Showcasing the latest advances in very-large-scale integrated (VLSI) circuits, VLSI: Circuits for Emerging Applications provides a balanced view of industrial and academic developments beyond silicon and complementary metal–oxide–semiconductor (CMOS) technology. From quantum-dot cellular automata (QCA) to chips for cochlear implants, this must-have resource: Investigates the trend of combining multiple cores in a single chip to boost performance of the overall system Describes a novel approach to enable physically unclonable functions (PUFs) using intrinsic features of a VLSI chip Examines the VLSI implementations of major symmetric and asymmetric key cryptographic algorithms, hash functions, and digital signatures Discusses nonvolatile memories such as resistive random-access memory (Re-RAM), magneto-resistive RAM (MRAM), and floating-body RAM (FB-RAM) Explores organic transistors, soft errors, photonics, nanoelectromechanical (NEM) relays, reversible computation, bioinformatics, asynchronous logic, and more VLSI: Circuits for Emerging Applications presents cutting-edge research, design architectures, materials, and uses for VLSI circuits, offering valuable insight into the current state of the art of micro- and nanoelectronics.
