Dynamic Fault Collapsing and Diagnostic Test Pattern Generation for Sequential Circuits PDF Download
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Author:
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Category :
Languages : en
Pages : 0
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Book Description
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by developing results that permit dynamic, fully functional, collapsing of candidate faults. Fault collapsing permits the organization of faults into disjoint partitions based on the indistinguishability relation. These results are used to develop a diagnostic test pattern generation algorithm that has the same order of complexity as that of detection oriented test generation (ATPG). Techniques to identify untestable faults, based on exploiting indistinguishability identification, are also presented. Experimental results are presented on the ISCAS 89 benchmark circuits.
Author:
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Category :
Languages : en
Pages : 0
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Book Description
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by developing results that permit dynamic, fully functional, collapsing of candidate faults. Fault collapsing permits the organization of faults into disjoint partitions based on the indistinguishability relation. These results are used to develop a diagnostic test pattern generation algorithm that has the same order of complexity as that of detection oriented test generation (ATPG). Techniques to identify untestable faults, based on exploiting indistinguishability identification, are also presented. Experimental results are presented on the ISCAS 89 benchmark circuits.
Author: Hyung Ki Lee
Publisher:
ISBN:
Category : Electric fault location
Languages : en
Pages : 390
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Book Description
Author: Andreas Kuehlmann
Publisher: Springer Science & Business Media
ISBN: 1461502926
Category : Computers
Languages : en
Pages : 699
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Book Description
In 2002, the International Conference on Computer Aided Design (ICCAD) celebrates its 20th anniversary. This book commemorates contributions made by ICCAD to the broad field of design automation during that time. The foundation of ICCAD in 1982 coincided with the growth of Large Scale Integration. The sharply increased functionality of board-level circuits led to a major demand for more powerful Electronic Design Automation (EDA) tools. At the same time, LSI grew quickly and advanced circuit integration became widely avail able. This, in turn, required new tools, using sophisticated modeling, analysis and optimization algorithms in order to manage the evermore complex design processes. Not surprisingly, during the same period, a number of start-up com panies began to commercialize EDA solutions, complementing various existing in-house efforts. The overall increased interest in Design Automation (DA) re quired a new forum for the emerging community of EDA professionals; one which would be focused on the publication of high-quality research results and provide a structure for the exchange of ideas on a broad scale. Many of the original ICCAD volunteers were also members of CANDE (Computer-Aided Network Design), a workshop of the IEEE Circuits and Sys tem Society. In fact, it was at a CANDE workshop that Bill McCalla suggested the creation of a conference for the EDA professional. (Bill later developed the name).
Author: N. K. Jha
Publisher: Cambridge University Press
ISBN: 9781139437431
Category : Computers
Languages : en
Pages : 1022
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Book Description
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Author:
Publisher:
ISBN:
Category : Application-specific integrated circuits
Languages : en
Pages : 504
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Book Description
Author:
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
ISBN: 9780769501468
Category : Computers
Languages : en
Pages : 534
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Book Description
The theme of the April 1999 symposium Scaling deeper to submicron: test technology challenges reflects the issues being created by the move toward nanometer technologies. Many creative and novel ideas and approaches to the current and future electronic circuit testing-related problems are explored
Author: Eugenio Villar Bonet
Publisher: Ed. Universidad de Cantabria
ISBN: 9788481022841
Category : Computers
Languages : en
Pages : 180
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Book Description
Este libro presenta los desafíos planteados por las nuevas y sumamente poderosas tecnologías de integración de sistemas electrónicos, que están en la base de los cambios sociales hacia lo que llaman la Sociedad de la Información; en la que los dispositivos electrónicos se harán una parte incorporada de la vida diaria, encajados en casi cada producto. Es necesario un conocimiento cuidadoso de los desafíos para aprovechar la amplia gama de ocasiones ofrecidas por tales capacidades de integración y las correspondientes posibilidades de diseño de sistemas electrónicos.
Author: B. D. Carroll
Publisher:
ISBN:
Category :
Languages : en
Pages : 25
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Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
Author: Salvador Bracho del Pino
Publisher: Ed. Universidad de Cantabria
ISBN: 9788481023114
Category : Technology & Engineering
Languages : en
Pages : 756
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Book Description
Este libro contiene las presentaciones de la XVII Conferencia de Diseño de Circuitos y Sistemas Integrados celebrado en el Palacio de la Magdalena, Santander, en noviembre de 2002. Esta Conferencia ha alcanzado un alto nivel de calidad, como consecuencia de su tradición y madurez, que lo convierte en uno de los acontecimientos más importantes para los circuitos de microelectrónica y la comunidad de diseño de sistemas en el sur de Europa. Desde su origen tiene una gran contribución de Universidades españolas, aunque hoy los autores participan desde catorce países
Author: Richard Saeks
Publisher: Marcel Dekker
ISBN:
Category : Business & Economics
Languages : en
Pages : 264
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Book Description
Information on the development of rational procedures for detection, location, & prediction of faults in a variety of systems. Includes a chapter on computer-aided fault analysis.
