Digital Background Calibration of a 10-b 40-MS/s Parallel Pipelined ADC PDF Download
Are you looking for read ebook online? Search for your book and save it on your Kindle device, PC, phones or tablets. Download Digital Background Calibration of a 10-b 40-MS/s Parallel Pipelined ADC PDF full book. Access full book title Digital Background Calibration of a 10-b 40-MS/s Parallel Pipelined ADC by Daihong Fu. Download full books in PDF and EPUB format.
Author: Daihong Fu
Publisher:
ISBN:
Category :
Languages : en
Pages : 254
Get Book Here
Book Description
Author: Daihong Fu
Publisher:
ISBN:
Category :
Languages : en
Pages : 254
Get Book Here
Book Description
Author: Pieter Harpe
Publisher: Springer
ISBN: 3319079387
Category : Technology & Engineering
Languages : en
Pages : 419
Get Book Here
Book Description
This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.
Author: Marcel J.M. Pelgrom
Publisher: Springer Science & Business Media
ISBN: 9048188881
Category : Technology & Engineering
Languages : en
Pages : 469
Get Book Here
Book Description
A book is like a window that allows you to look into the world. The window is shaped by the author and that makes that every window presents a unique view of the world. This is certainly true for this book. It is shaped by the topics and the projects throughout my career. Even more so, this book re?ects my own style of working and thinking. That starts already in Chap. 2. When I joined Philips Research in 1979, many of my colleagues used little paper notebooks to keep track of the most used equations and other practical things. This notebook was the beginning for Chap. 2: a collection of topics that form the basis for much of the other chapters. Chapter2 is not intended to explain these topics, but to refresh your knowledge and help you when you need some basics to solve more complex issues. In the chapters discussing the fundamental processes of conversion, you will r- ognize my preoccupation with mathematics. I really enjoy ?nding an equation that properly describes the underlying mechanism. Nevertheless mathematics is not a goalonitsown:theequationshelptounderstandthewaythevariablesareconnected to the result. Real insight comes from understanding the physics and electronics. In the chapters on circuit design I have tried to reduce the circuit diagrams to the s- plest form, but not simpler. . . I do have private opinions on what works and what should not be applied.
Author: Mikko E. Waltari
Publisher: Springer Science & Business Media
ISBN: 0306479796
Category : Technology & Engineering
Languages : en
Pages : 256
Get Book Here
Book Description
This useful monograph presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques.
Author: Kenneth Colin Dyer
Publisher:
ISBN:
Category : Analog-to-digital converters
Languages : en
Pages : 300
Get Book Here
Book Description
Author: João Goes
Publisher: Springer Science & Business Media
ISBN: 0306481936
Category : Technology & Engineering
Languages : en
Pages : 171
Get Book Here
Book Description
This excellent reference proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. The book may also be used as a text for advanced reading on the subject.
Author: Amir Zjajo
Publisher: Springer Science & Business Media
ISBN: 9048197252
Category : Technology & Engineering
Languages : en
Pages : 311
Get Book Here
Book Description
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Author: Sudipta Sarkar
Publisher:
ISBN:
Category : Comparator circuits
Languages : en
Pages :
Get Book Here
Book Description
A digital background calibration technique to treat capacitor mismatch, residue gain error and nonlinearity in a pipelined analog-to-digital converter (ADC) based on the split-ADC architecture (J. McNeill et al., “Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,” IEEE J. of Solid-State Circuits, vol. 40, pp. 2437-2445, Dec. 2005) is reported. Although multiple works have been reported before on the split-calibration of pipelined analog-to-digital converters, none of them is comprehensive, i.e., capacitor mismatch, residue gain error and nonlinearity are never treated in one work at the same time. We, for the first time, recognize the multistage pipelined ADC with residue non-linearity calibration as a Nonlinear Least Squares problem. Behavioral simulation results demonstrate the efficacy of the technique, in which the signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) performance of a 15-bit split-pipelined ADC are improved from 42 dB and 50 dB to 88 dB and 102 dB on average, respectively. Secondly, an 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing with an area-efficient 8b offset calibration DAC. A prototype in 28nm Complementary Metal Oxide Semiconductor (CMOS) achieves 6.8 effective number of bits (ENOB) and 50fJ/c-s at DC and 6.3 ENOB and 68fJ/c-s at Nyquist, at a sample rate of 1.3GS/s. The measured SNDR/SFDR improve from 29.2/40.7dB to 42.6/57.7dB after calibration. The active area is 0.05mm2.
Author: Yu Lin
Publisher: Springer
ISBN: 3319176803
Category : Technology & Engineering
Languages : en
Pages : 124
Get Book Here
Book Description
This book addresses the challenges of designing high performance analog-to-digital converters (ADCs) based on the “smart data converters” concept, which implies context awareness, on-chip intelligence and adaptation. Readers will learn to exploit various information either a-priori or a-posteriori (obtained from devices, signals, applications or the ambient situations, etc.) for circuit and architecture optimization during the design phase or adaptation during operation, to enhance data converters performance, flexibility, robustness and power-efficiency. The authors focus on exploiting the a-priori knowledge of the system/application to develop enhancement techniques for ADCs, with particular emphasis on improving the power efficiency of high-speed and high-resolution ADCs for broadband multi-carrier systems.
Author: Xiaoyue Wang
Publisher:
ISBN:
Category :
Languages : en
Pages : 270
Get Book Here
Book Description
