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Author: Yuan Xie
Publisher: Springer Nature
ISBN: 3031017471
Category : Technology & Engineering
Languages : en
Pages : 113
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Book Description
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
Author: Yuan Xie
Publisher: Springer Nature
ISBN: 3031017471
Category : Technology & Engineering
Languages : en
Pages : 113
Get Book Here
Book Description
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
Author: Yuan Xie
Publisher: Morgan & Claypool Publishers
ISBN: 1627057668
Category : Computers
Languages : en
Pages : 129
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Book Description
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
Author: Hafizur Rahaman
Publisher: Springer
ISBN: 3642314945
Category : Computers
Languages : en
Pages : 427
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Book Description
This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The papers are organized in topical sections on VLSI design, design and modeling of digital circuits and systems, testing and verification, design for testability, testing memories and regular logic arrays, embedded systems: hardware/software co-design and verification, emerging technology: nanoscale computing and nanotechnology.
Author: Vinod Pangracious
Publisher: Springer
ISBN: 3319191748
Category : Technology & Engineering
Languages : en
Pages : 239
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Book Description
This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and professionals alike.
Author: Bhavani Prasad Dewan Sandur
Publisher: ProQuest
ISBN: 9780542810671
Category : Mechanical engineering
Languages : en
Pages :
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Book Description
This thesis focuses on carrying out a parametric study of stacking memory and the logic processor on the same substrate. In present technologies, logic processor and memory packages are located side-by-side on the board or they are packaged separately and then stacked on top of each other (Package-on-package [PoP]). Mixing memory and logic processor in the same stack has advantage and challenges, but requires the integration ability of economies-of-scale. The technology needed for packaging memory and logic dice on the same substrate is completely different as compared to packaging only memory dice or logic dice, or, packaging memory and logic separately and creating a single functional package [PoP]. Geometries needed were generated by using Pro/EngineerRTM Wildfire(TM) 2.0 as a Computer-Aided-Design (CAD) tool and were transferred to ANSYSRTM Workbench(TM) 10.0, where meshed analysis was conducted. Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant. The values of these parameters were determined to give a junction temperature of 100°C, which is an unacceptable value due to wafer level electromigration. A discussion is presented as to what parameters need to be adjusted in order to meet the required thermal design specification. In that light, a list of solutions consisting of increasing the heat transfer co-efficient on top of the package, the use of underfill, improved thermal conductivity of the PCB, and the use of a copper heat spreader were evaluated. Results are evaluated in the light of market segment requirements. (Abstract shortened by UMI.).
Author: Paul D. Franzon
Publisher: John Wiley & Sons
ISBN: 3527338551
Category : Technology & Engineering
Languages : en
Pages : 488
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Book Description
This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.
Author: Rajeev Balasubramonian
Publisher: Morgan & Claypool Publishers
ISBN: 9781598297539
Category : Computers
Languages : en
Pages : 137
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Book Description
A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints.The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research.The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers.Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks
Author: David Kaeli
Publisher: Springer
ISBN: 3540937994
Category : Computers
Languages : en
Pages : 153
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Book Description
This book constitutes the proceedings of the SPEC Benchmark Workshop 2009 held in Austin, Texas, USA on January 25th, 2009. The 9 papers presented were carefully selected and reviewed for inclusion in the book. The result is a collection of high-quality papers discussing current issues in the area of benchmarking research and technology. The topics covered are: benchmark suites, CPU benchmarking, power/thermal benchmarking, and modeling and sampling techniques.
Author: Weixia Xu
Publisher: Springer
ISBN: 3662492830
Category : Computers
Languages : en
Pages : 197
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Book Description
This book constitutes the refereed proceedings of the 19th CCF Conference on Computer Engineering and Technology, NCCET 2015, held in Hefei, China, in October 2015. The 18 papers presented were carefully reviewed and selected from 158 submissions. They are organized in topical sections on processor architecture; application specific processors; computer application and software optimization; technology on the horizon.
Author: Luís Miguel Pinho Pinho
Publisher: Springer
ISBN: 3319160869
Category : Computers
Languages : en
Pages : 255
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Book Description
This book constitutes the proceedings of the 28th International Conference on Architecture of Computing Systems, ARCS 2015, held in Porto, Portugal, in March 2015. The 19 papers presented together with three invited papers were carefully reviewed and selected from 45 submissions. The papers are organized in six sessions covering the topics: hardware, design, applications, trust and privacy, real-time issues and a best papers session.
