Author: Amos R. Omondi
Publisher: Springer Science & Business Media
ISBN: 0387284877
Category : Technology & Engineering
Languages : en
Pages : 365
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Book Description
During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.
Author: Ee Ric Lim
Publisher:
ISBN:
Category : Field programmable gate arrays
Languages : en
Pages : 0
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Book Description
Author: Erwei Wang
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
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Book Description
Author: Peter Y.K. Cheung
Publisher: Springer Science & Business Media
ISBN: 3540408223
Category : Computers
Languages : en
Pages : 1204
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Book Description
This book constitutes the refereed proceedings of the 13th International Conference on Field-Programmable Logic and Applications, FPL 2003, held in Lisbon, Portugal in September 2003. The 90 revised full papers and 56 revised poster papers presented were carefully reviewed and selected from 216 submissions. The papers are organized in topical sections on technologies and trends, communications applications, high level design tools, reconfigurable architecture, cryptographic applications, multi-context FPGAs, low-power issues, run-time reconfiguration, compilation tools, asynchronous techniques, bio-related applications, codesign, reconfigurable fabrics, image processing applications, SAT techniques, application-specific architectures, DSP applications, dynamic reconfiguration, SoC architectures, emulation, cache design, arithmetic, bio-inspired design, SoC design, cellular applications, fault analysis, and network applications.
Author: Irwin King
Publisher: Springer Science & Business Media
ISBN: 3540464840
Category : Artificial intelligence
Languages : en
Pages : 1248
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Book Description
Annotation The three volume set LNCS 4232, LNCS 4233, and LNCS 4234 constitutes the refereed proceedings of the 13th International Conference on Neural Information Processing, ICONIP 2006, held in Hong Kong, China in October 2006. The 386 revised full papers presented were carefully reviewed and selected from 1175 submissions. The 126 papers of the first volume are organized in topical sections on neurobiological modeling and analysis, cognitive processing, mathematical modeling and analysis, learning algorithms, support vector machines, self-organizing maps, as well as independent component analysis and blind source separation. The second volume contains 128 contributions related to pattern classification, face analysis and processing, image processing, signal processing, computer vision, data pre-processing, forecasting and prediction, as well as neurodynamic and particle swarm optimization. The third volume offers 131 papers that deal with bioinformatics and biomedical applications, information security, data and text processing, financial applications, manufacturing systems, control and robotics, evolutionary algorithms and systems, fuzzy systems, and hardware implementations.
Author: Jaber Salem
Publisher:
ISBN:
Category :
Languages : en
Pages : 160
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Book Description
In contrast with analog design, digital design and implementation of any logic circuit suffer much from the difficulty in terms of economy and implementation. Neural networks are artificial systems inspired by the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as, optimization problems, text and speech recognition. Since the topology of neural networks is highly crucial to the performance, the reconfigurable ability of the neural network hardware is very essential. Reconfigurability factually means several different designs can be implemented on a single architecture. Therefore, this work proposes an efficient architecture to implement the reconfigurable back propagation and Hopfield neural networks. We specifically adopted the reconfigurable artificial neural networks approach to show how it is possible to build an efficient chip. Simple neural network models with an appropriate training were used to behave as traditional logic functions in the bit- level. In order to further reduce the hardware, memories-sharing method has been adopted. Also, a comparison between the proposed and traditional networks shows that the proposed network has significantly reduced the time delay and power consumption. Xilinx - ISE is used to synthesize our design. VHDL code is used to build the architecture. The architecture code is then downloaded to FPGAs (Field Programmable Gate Array) to implement the design. FPGAs are strong tools to implement ANNs as one can exploit concurrency and rapidly reconfigure to adapt the weights and topologies of an ANN. Also, XPower, as one of the best tools in Xilinx, was used to measure the total required power by our architecture. Finally, the results showed that the proposed reconfigurable architecture leads to a considerable decrease in the consumed power to almost 43% as well as the total time delay. Also, the architecture can easily be scalable as a future work and is able to cope with several network sizes with the same hardware.
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Author: Vivienne Sze
Publisher: Springer Nature
ISBN: 3031017668
Category : Technology & Engineering
Languages : en
Pages : 254
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Book Description
This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas.
Author: Parviz Michael Palangpour
Publisher:
ISBN:
Category : Field programmable gate arrays
Languages : en
Pages : 0
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Book Description
"This thesis describes the Field Programmable Gate Array (FPGA) implementations of two powerful techniques of Computational Intelligence (CI), the Particle Swarm Optimization algorithm (PSO) and the Neural Network (NN). Particle Swarm Optimization (PSO) is a popular population-based optimization algorithm. While PSO has been shown to perform well in a large variety of problems, PSO is typically implemented in software. Population-based optimization algorithms such as PSO are well suited for execution in parallel stages. This allows PSO to be implemented directly in hardware and achieve much faster execution times than possible in software. In this thesis, a pipelined architecture for hardware PSO implementation is presented. Benchmark functions solved by software and FPGA hardware PSO implementations are compared. NNs are inherently parallel, with each layer of neurons processing incoming data independently of each other. While general purpose processors have reached impressive processing speeds, they still cannot fully exploit this inherent parallelism due to their sequential architecture. In order to achieve the high neural network throughput needed for real-time applications, a custom hardware design is needed. In this thesis, a digital implementation of an NN is developed for FPGA implementation. The hardware PSO implementation is designed using only VHDL, while the NN hardware implementation is designed using Xilinx System Generator. Both designs are synthesized using Xilinx ISE and implemented on the Xilinx Virtex-II Pro FPGA Development Kit"--Abstract, leaf iii
Author: Jonathan Turner
Publisher:
ISBN:
Category : Electronic dissertations
Languages : en
Pages : 114
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Book Description
Author's abstract: This work documents a study of intelligent neural network control system design and implementation for engineering applications. In this study, the effectiveness of single multiplicative neuron (SMN) in place of traditional multi-layer perceptron (MLP) is investigated. The objectives were to (i) verify the feasibility of SMN based control systems, (ii) quantitatively compare the performance of SMN and MLP based systems, (iii) determine the amount of computation that could be saved by using SMN instead of MLP in a control system, and (iv) determine the performance of a SMN in an adaptive critic design (ACD) using action dependent heuristic dynamic programming (ADHDP). It was hypothesized that the replacement of a MLP network with a SMN would result in a controller that would achieve the same control quality in a less processor intensive manner, possibly allowing controller implementation on a less costly computer or microcontroller system. Controllers featuring the MLP and the SMN were implemented in LabVIEW for two physical systems and compared based on their ability to accurately control the system response when given complex reference inputs. The SMN based control systems were implemented with both off-line and on-line training using conventional and field programmable gate array (FPGA) based data acquisition hardware. The controllers were also compared based on the number of calculations required to complete the artificial neural network (ANN) related sections of the control loop. The SMN based control systems were found to perform as well as, if not better than their MLP based counterparts, in all cases studied, while significantly reducing required computations. The SMN was finally implemented in an intelligent controller based on ADHDP and found to perform better than conventional controllers like PID with a periodic disturbance.
