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Author: Nazar Abbas Zaidi
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 294
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Book Description
Author: Nazar Abbas Zaidi
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 294
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Book Description
Author: Rolf Drechsler
Publisher: Springer Science & Business Media
ISBN: 9048123607
Category : Technology & Engineering
Languages : en
Pages : 196
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Book Description
In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.
Author: Muhammad Nazir Mohammed Khalid
Publisher:
ISBN:
Category : Automatic control
Languages : en
Pages : 186
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Book Description
With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. To ease testing, digital systems are commonly designed with Built-In Self Test facility. For this reason, development of test pattern for BIST based on combination of Linear Feedback Shift Register (LFSR) and deterministic ATPG (DATPG) approach could provide more solutions, such as reduce testing time, high fault coverage and low area overhead. One of the key challenges in BIST is the design of the Test Pattern Generation (TPG) that promised high fault coverage. The test pattern generation can be generated either manually or automatically. Problems related to ATPG are linked to the controllability and observability of the nodes in circuits. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational circuit. To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. Altera Max+plus II software is used to simulate the DATPG design to achieve the minimum test patterns for digital combinational circuit. The simulation result will be presented in the form of waveform. The results of DATPG for digital combinational circuit show that the sequence of LFSR has been reduced significantly. In BIST application, the minimum test patterns are applied to the adder/substractor (A/S) known as circuit under test (CUT). A parallel A/S is chosen as a CUT due to the simplicity of the circuit architecture. The A/S is used to verify the proposed DATPG performance. Only one basic cell of the parallel A/S is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both A/S inputs simultaneously. By reducing the number of test pattern, the testing time to market and manufacturing time is expected to reduce leading to reduction in the product cost.
Author:
Publisher:
ISBN:
Category : Computers
Languages : en
Pages : 152
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Book Description
Author: Matteo Sonza Reorda
Publisher: Springer Science & Business Media
ISBN: 1846281458
Category : Technology & Engineering
Languages : en
Pages : 187
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Book Description
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue. This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability.
Author: Juan C. López
Publisher: Springer Science & Business Media
ISBN: 1475744196
Category : Computers
Languages : en
Pages : 298
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Book Description
As electronic technology reaches the point where complex systems can be integrated on a single chip, and higher degrees of performance can be achieved at lower costs, designers must devise new ways to undertake the laborious task of coping with the numerous, and non-trivial, problems that arise during the conception of such systems. On the other hand, shorter design cycles (so that electronic products can fit into shrinking market windows) put companies, and consequently designers, under pressure in a race to obtain reliable products in the minimum period of time. New methodologies, supported by automation and abstraction, have appeared which have been crucial in making it possible for system designers to take over the traditional electronic design process and embedded systems is one of the fields that these methodologies are mainly targeting. The inherent complexity of these systems, with hardware and software components that usually execute concurrently, and the very tight cost and performance constraints, make them specially suitable to introduce higher levels of abstraction and automation, so as to allow the designer to better tackle the many problems that appear during their design. Advanced Techniques for Embedded Systems Design and Test is a comprehensive book presenting recent developments in methodologies and tools for the specification, synthesis, verification, and test of embedded systems, characterized by the use of high-level languages as a road to productivity. Each specific part of the design process, from specification through to test, is looked at with a constant emphasis on behavioral methodologies. Advanced Techniques for Embedded Systems Design and Test is essential reading for all researchers in the design and test communities as well as system designers and CAD tools developers.
Author: Kyuchull Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 348
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Book Description
Author: Hans-Joachim Wunderlich
Publisher: Springer Science & Business Media
ISBN: 9048132827
Category : Computers
Languages : en
Pages : 263
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Book Description
Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.
Author: Luciano Lavagno
Publisher: CRC Press
ISBN: 1482254638
Category : Technology & Engineering
Languages : en
Pages : 644
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Book Description
The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.
Author: Zebo Peng
Publisher: Springer Science & Business Media
ISBN: 9781852338992
Category : Computers
Languages : en
Pages : 206
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Book Description
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue. This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability.
