Author: Alexandre RaymondPublisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
"Polar codes are a new class of forward error-correcting codes recently discovered by Arıkan. They are the first codes with an explicit construction to provably achieve capacity, a theoretical limit governing the transmission of information in the presence of noise, for a wide variety of communication channels. Since polar codes have a very regular construction, they also lend themselves very well to hardware implementations. This thesis presents the design work underlying the development of two generations of hardware decoders for polar codes based upon the successive-cancellation algorithm. Making use of SRAM-based semi-parallel architectures, those designs allow very large polar codes to be implemented on Altera Stratix IV and Stratix V FPGA targets: up to N=2 17 for the first generation, and N=2 21 for the second-generation design. The second-generation decoder also features variable quantization levels to reduce its memory footprint, look-ahead to improve throughput, a redesigned partial-sum encoder based on a novel semi-parallel design for increased scalability, and an overlapped frame loading mechanism allowing full-speed operation of the decoder with a single input buffer." --
