Delay Testing of Digital Circuits Using Pseudorandom Input Sequences

Delay Testing of Digital Circuits Using Pseudorandom Input Sequences PDF Author: Stanford University. Computer Systems Laboratory
Publisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 34

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Book Description

Delay Testing of Digital Circuits Using Pseudorandom Input Sequences

Delay Testing of Digital Circuits Using Pseudorandom Input Sequences PDF Author: Stanford University. Computer Systems Laboratory
Publisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 34

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Book Description


Delay Testing of Digital Circuits Using Pseudorandom Input Sequences

Delay Testing of Digital Circuits Using Pseudorandom Input Sequences PDF Author: Kenneth D. Wagner
Publisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 37

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Book Description


Testing and Reliable Design of CMOS Circuits

Testing and Reliable Design of CMOS Circuits PDF Author: Niraj K. Jha
Publisher: Springer Science & Business Media
ISBN: 1461315255
Category : Computers
Languages : en
Pages : 239

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Book Description
In the last few years CMOS technology has become increas ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den sity and low power requirement. The ability to realize very com plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.

Random Testing of Digital Circuits

Random Testing of Digital Circuits PDF Author: Rene David
Publisher: CRC Press
ISBN: 1000146014
Category : Technology & Engineering
Languages : en
Pages : 508

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Book Description
"Introduces a theory of random testing in digital circuits for the first time and offers practical guidance for the implementation of random pattern generators, signature analyzers design for random testability, and testing results. Contains several new and unpublished results. "

An Introduction to Logic Circuit Testing

An Introduction to Logic Circuit Testing PDF Author: Parag K. Lala
Publisher: Morgan & Claypool Publishers
ISBN: 1598293508
Category : Computers
Languages : en
Pages : 111

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Book Description
An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems

Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems PDF Author: Fevzi Belli
Publisher: Springer Science & Business Media
ISBN: 3642456286
Category : Computers
Languages : en
Pages : 401

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Book Description
Dieser Band enthält die 38 Beiträge der 3. GI/ITG/GMA-Fachtagung über "Fehlertolerierende Rechensysteme". Unter den 10 aus dem Ausland eingegangenen Beiträgen sind 4 eingeladene Vorträge. Insgesamt dokumentiert dieser Tagungsband die Entwicklung der Konzeption und Implementierung fehlertoleranter Systeme in den letzten drei Jahren vor allem in Europa. Sämtliche Beiträge sind neue Forschungs- oder Entwicklungsergebnisse, die vom Programmausschuß der Tagung aus 70 eingereichten Beiträgen ausgewählt wurden.

Random Testing of Digital Circuits

Random Testing of Digital Circuits PDF Author: Rene David
Publisher: CRC Press
ISBN: 1000110168
Category : Technology & Engineering
Languages : en
Pages : 496

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Book Description
"Introduces a theory of random testing in digital circuits for the first time and offers practical guidance for the implementation of random pattern generators, signature analyzers design for random testability, and testing results. Contains several new and unpublished results. "

Built In Test for VLSI

Built In Test for VLSI PDF Author: Paul H. Bardell
Publisher: Wiley-Interscience
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 376

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Book Description
This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing.

Testing of Digital Systems

Testing of Digital Systems PDF Author: N. K. Jha
Publisher: Cambridge University Press
ISBN: 9781139437431
Category : Computers
Languages : en
Pages : 1022

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Book Description
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

Contactless VLSI Measurement and Testing Techniques

Contactless VLSI Measurement and Testing Techniques PDF Author: Selahattin Sayil
Publisher: Springer
ISBN: 3319696734
Category : Technology & Engineering
Languages : en
Pages : 92

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Book Description
This book provides readers with a comprehensive overview of the state-of-the-art in optical contactless probing approaches, in order to fill a gap in the literature on VLSI Testing. The author highlights the inherent difficulties encountered with the mechanical probe and testability design approaches for functional and internal fault testing and shows how contactless testing might resolve many of the challenges associated with conventional mechanical wafer testing. The techniques described in this book address the increasing demands for internal access of the logic state of a node within a chip under test.