Automatic test pattern generation for hierarchical sequential circuits PDF Download
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Author: Heinrich Theodor Vierhaus
Publisher:
ISBN:
Category :
Languages : de
Pages : 19
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Author: Heinrich Theodor Vierhaus
Publisher:
ISBN:
Category :
Languages : de
Pages : 19
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Author: Anna Rannaste
Publisher:
ISBN: 9789949230419
Category :
Languages : en
Pages : 127
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Author: Marinus Hendrik Konijnenburg
Publisher:
ISBN: 9789090120966
Category :
Languages : en
Pages : 226
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Author: Vojin G. Oklobdzija
Publisher: CRC Press
ISBN: 9780849308857
Category : Computers
Languages : en
Pages : 1422
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Book Description
There is arguably no field in greater need of a comprehensive handbook than computer engineering. The unparalleled rate of technological advancement, the explosion of computer applications, and the now-in-progress migration to a wireless world have made it difficult for engineers to keep up with all the developments in specialties outside their own. References published only a few years ago are now sorely out of date. The Computer Engineering Handbook changes all of that. Under the leadership of Vojin Oklobdzija and a stellar editorial board, some of the industry's foremost experts have joined forces to create what promises to be the definitive resource for computer design and engineering. Instead of focusing on basic, introductory material, it forms a comprehensive, state-of-the-art review of the field's most recent achievements, outstanding issues, and future directions. The world of computer engineering is vast and evolving so rapidly that what is cutting-edge today may be obsolete in a few months. While exploring the new developments, trends, and future directions of the field, The Computer Engineering Handbook captures what is fundamental and of lasting value.
Author: Chun-Hung Chen
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 188
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Author: Debashis Bhattacharya
Publisher: Springer Science & Business Media
ISBN: 1461315271
Category : Computers
Languages : en
Pages : 168
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Book Description
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
Author: Byungse So
Publisher:
ISBN:
Category :
Languages : en
Pages : 296
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Author: Jessica L. Handy
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
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Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 88
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Author: Catherine H. Gebotys
Publisher: Springer Science & Business Media
ISBN: 1461540186
Category : Technology & Engineering
Languages : en
Pages : 293
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Book Description
Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.
