Automatic Test Generation Techniques for Sequential Circuits PDF Download
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Author: Xiaoming Yu
Publisher:
ISBN:
Category :
Languages : en
Pages : 214
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Book Description
Author: Xiaoming Yu
Publisher:
ISBN:
Category :
Languages : en
Pages : 214
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Book Description
Author: Thomas E. Marchok
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 138
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Book Description
Abstract: "Several manufacturing challenges have accompanied the explosive growth in the scale of integration for VLSI circuits. One of these is the increased difficulty of generating manufacturing test sets, which has resulted from the vast increase in the ratio of the number of transistors to the number of I/O pins. The difficulty of test generation is crucial since it impacts both the resultant product quality and time to market, both of which continue to gain importance in the present day semiconductor industry. Design for testability (DFT) techniques can be used to offset this difficulty. The mechanics of such techniques are well understood. DFT techniques are also known to increase other manufacturing costs and to decrease performance. Thus the relevant issue facing designers is not how to use DFT, but rather if such techniques should be applied. The correct decision is a matter of economics. Integrated circuit (IC) designers must balance manufacturing costs, performance, time to market, and product quality concerns. Achieving the desired balance requires the ability to quantify trade-offs in the different manufacturing costs which various DFT techniques would affect. Unfortunately, test generation cost is among the least predictable of these affected costs, even though the principal reason that DFT techniques are often applied is to reduce the difficulty of test generation. Furthermore, there does not exist a complete understanding of which circuit attributes influence the difficulty of test generation. In this thesis, a model is developed which predicts the difficulty of automatic test generation for non-scan sequential circuits. This model is based on a newly recognized circuit attribute, termed density of encoding, which differs from those notions which have been used to describe this difficulty in the past. This thesis also discusses how the concept of the density of encoding can be applied to devise more powerful sequential automatic test pattern generation algorithms, more efficient DFT techniques, and more effective synthesis for testability schemes."
Author: Thomas Michael Niermann
Publisher:
ISBN:
Category :
Languages : en
Pages : 212
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Book Description
Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a combinational circuit for testing purposes, the cost of a complete scan design methodology can be prohibitive in both area overhead and performance degradation. Therefore, an efficient sequential circuit test generation system which generates tests for all detectable faults and identifies all untestable faults in the original design is necessary. The information on untestable faults could be used to add minimal design for test hardware to make these faults testable. This thesis presents several new techniques to improve the performance of sequential circuit test generators. Among the concepts presented are unnecessary state elimination, and the use of fault simulation knowledge to increase test coverage during a second phase of test generation, a targeted D element technique for D propagation, and the use of the good circuit state knowledge. The concepts presented in the thesis were implemented and tested on the ISCAS sequential benchmark circuits. This thesis presents an improved fault simulation algorithm based on a combination of the parallel, concurrent and differential fault simulation algorithms. This fault simulator is shown to require much less memory while being 6 to 67 times faster than a traditional concurrent fault simulator.
Author: G. Russell
Publisher: Springer Science & Business Media
ISBN: 9780747600015
Category : Computers
Languages : en
Pages : 406
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Book Description
Author: Venkat N. Koripalli
Publisher:
ISBN:
Category :
Languages : en
Pages : 74
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Book Description
The increase in speed and the shrinking of technology has led to modern day ICs becoming more sensitive to timing related defects. These defects must be rectified to prevent hazards in the circuit. The timing related defects can be identified with At-Speed Testing using the path delay fault model. A subset of the total number of paths known as critical paths cannot be sequentially activated i.e. we cannot find two successive vectors that activate a fault along the path. The elimination of untestable paths helps us to save a lot of time. In this report a new method, called the Launch-on-Shift is used to determine the testability of critical paths. The method uses a vector pair in which the first vector is the scan in steady state vector and the second vector is the function of the first vector.
Author: Soo Y. Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 252
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Book Description
Author: Francis C. Wong
Publisher: Elsevier
ISBN: 0080504345
Category : Technology & Engineering
Languages : en
Pages : 248
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Book Description
Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to these and other testing techniques. For each technique introduced, the author provides real-world examples so the reader can achieve a working knowledge of how to choose and apply these increasingly important testing methods.
Author: Louis Scheffer
Publisher: CRC Press
ISBN: 1351837591
Category : Technology & Engineering
Languages : en
Pages : 593
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Book Description
Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.
Author: Luciano Lavagno
Publisher: CRC Press
ISBN: 1351830996
Category : Technology & Engineering
Languages : en
Pages : 773
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Book Description
The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.
Author: Rajen Sham Ramchandani
Publisher:
ISBN:
Category : Digital electronics
Languages : en
Pages : 174
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Book Description
Abstract: "The goal of this thesis is to exploit the design hierarchy to solve the problem of test vector generation for sequential circuits. The fault model used for sequential test vector generation is the single stuck-at fault model. This thesis describes a bottom-up hierarchical test vector generation technique to generate test vectors using the behavioral description of the circuit function. This work uses the linking information generated by the high-level synthesis tool which allows traversal of the design hierarchy between the behavioral level, the RTL and the gate-level. Gate-level test vectors for individual modules are sensitized and propagated at the behavioral-level. The fault sensitization and the fault propagation techniques are developed from software testing techniques and generate a system of equations. This system of equations is transformed into a Mixed Integer Non-Linear Programming problem and solved to obtain the test vectors. The technique has been implemented and results from this approach show an order of magnitude speed up in test generation compared to existing gate-level sequential test generation tools."
