Analysis and Code Generation for Multicore Fault Tolerant Mixed Criticality Embedded Systems PDF Download
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Author: Jonah Caplan
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
"Safety critical embedded systems often require redundant hardware to guarantee correct operation. Typically, in the automotive domain, redundancy is implemented using a pair of cores executing in lockstep to achieve dual modular redundancy. Lockstep execution, however, has been shown in theory to be less efficient than alternative redundancy schemes such as on-demand redundancy, where redundancy is achieved by replicating threads in a multicore system. In this thesis, an analysis and code generation framework is presented which automates the porting of Simulink generated code to a previously implemented multicore architecture supporting ODR with fingerprinting hardware to detect errors.The framework consists of three stages: first a profiling stage where information is collected on execution time, then a mapping and scheduling phase where resources are allocated in a safe manner, and finally the generation of the code itself. A framework has been implemented to allow arbitrary intraprocedural analysis to be defined for a program compiled for the Nios II architecture. An analysis has been implemented using the framework to determine the worst case behaviour of loops. The instruction-accurate worst case execution time (WCET) of each function is then estimated using the standard implicit path enumeration technique. A novel four mode multicore schedulability analysis is presented for mixed criticality fault tolerant systems which improves the quality of service in the presence of faults or execution time overruns. The schedulability analysis is integrated with a design space exploration framework that uses genetic algorithms to determine schedules with better quality of service. Code generation targets a previously designed multicore platform with Nios II processors and fingerprinting based error detection to automate the porting of Simulink generated control algorithms onto the platform. The generated code is verified on a virtual model of the platform implemented with Open Virtual Platform. Future work will include verifying the code on FPGA and calibrate the WCET estimation to reflect non-ideal memory retrieval." --
Author: Jonah Caplan
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
"Safety critical embedded systems often require redundant hardware to guarantee correct operation. Typically, in the automotive domain, redundancy is implemented using a pair of cores executing in lockstep to achieve dual modular redundancy. Lockstep execution, however, has been shown in theory to be less efficient than alternative redundancy schemes such as on-demand redundancy, where redundancy is achieved by replicating threads in a multicore system. In this thesis, an analysis and code generation framework is presented which automates the porting of Simulink generated code to a previously implemented multicore architecture supporting ODR with fingerprinting hardware to detect errors.The framework consists of three stages: first a profiling stage where information is collected on execution time, then a mapping and scheduling phase where resources are allocated in a safe manner, and finally the generation of the code itself. A framework has been implemented to allow arbitrary intraprocedural analysis to be defined for a program compiled for the Nios II architecture. An analysis has been implemented using the framework to determine the worst case behaviour of loops. The instruction-accurate worst case execution time (WCET) of each function is then estimated using the standard implicit path enumeration technique. A novel four mode multicore schedulability analysis is presented for mixed criticality fault tolerant systems which improves the quality of service in the presence of faults or execution time overruns. The schedulability analysis is integrated with a design space exploration framework that uses genetic algorithms to determine schedules with better quality of service. Code generation targets a previously designed multicore platform with Nios II processors and fingerprinting based error detection to automate the porting of Simulink generated control algorithms onto the platform. The generated code is verified on a virtual model of the platform implemented with Open Virtual Platform. Future work will include verifying the code on FPGA and calibrate the WCET estimation to reflect non-ideal memory retrieval." --
Author: Behnaz Ranjbar
Publisher: Springer Nature
ISBN: 3031389603
Category : Technology & Engineering
Languages : en
Pages : 205
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Book Description
This book addresses the challenges associated with efficient Mixed-Criticality (MC) system design. We focus on application analysis through execution time analysis and task scheduling analysis in order to execute more low-criticality tasks in the system, i.e., improving the Quality-of-Service (QoS), while guaranteeing the correct execution of high-criticality tasks. Further, this book addresses the challenge of enhancing QoS using parallelism in multi-processor hardware platforms.
Author: Massimo Torquati
Publisher: Springer Science & Business Media
ISBN: 1461488001
Category : Technology & Engineering
Languages : en
Pages : 194
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Book Description
This book provides a single-source reference to the state-of-the-art of high-level programming models and compilation tool-chains for embedded system platforms. The authors address challenges faced by programmers developing software to implement parallel applications in embedded systems, where very often they are forced to rewrite sequential programs into parallel software, taking into account all the low level features and peculiarities of the underlying platforms. Readers will benefit from these authors’ approach, which takes into account both the application requirements and the platform specificities of various embedded systems from different industries. Parallel programming tool-chains are described that take as input parameters both the application and the platform model, then determine relevant transformations and mapping decisions on the concrete platform, minimizing user intervention and hiding the difficulties related to the correct and efficient use of memory hierarchy and low level code generation.
Author: Georgios Kornaros
Publisher: CRC Press
ISBN: 1439811628
Category : Computers
Languages : en
Pages : 502
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Book Description
Details a real-world product that applies a cutting-edge multi-core architecture Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner. Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth. Discusses the available programming models spread across different abstraction levels The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as: Architectures and interconnects Embedded design methodologies Mapping of applications
Author: Max Domeika
Publisher: Newnes
ISBN: 0080558585
Category : Technology & Engineering
Languages : en
Pages : 435
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Book Description
The multicore revolution has reached the deployment stage in embedded systems ranging from small ultramobile devices to large telecommunication servers. The transition from single to multicore processors, motivated by the need to increase performance while conserving power, has placed great responsibility on the shoulders of software engineers. In this new embedded multicore era, the toughest task is the development of code to support more sophisticated systems. This book provides embedded engineers with solid grounding in the skills required to develop software targeting multicore processors. Within the text, the author undertakes an in-depth exploration of performance analysis, and a close-up look at the tools of the trade. Both general multicore design principles and processor-specific optimization techniques are revealed. Detailed coverage of critical issues for multicore employment within embedded systems is provided, including the Threading Development Cycle, with discussions of analysis, design, development, debugging, and performance tuning of threaded applications. Software development techniques engendering optimal mobility and energy efficiency are highlighted through multiple case studies, which provide practical “how-to advice on implementing the latest multicore processors. Finally, future trends are discussed, including terascale, speculative multithreading, transactional memory, interconnects, and the software-specific implications of these looming architectural developments. This is the only book to explain software optimization for embedded multi-core systems Helpful tips, tricks and design secrets from an Intel programming expert, with detailed examples using the popular X86 architecture Covers hot topics, including ultramobile devices, low-power designs, Pthreads vs. OpenMP, and heterogeneous cores
Author: Abderazek Ben Abdallah
Publisher: Springer
ISBN: 9811060924
Category : Computers
Languages : en
Pages : 292
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Book Description
From basic architecture, interconnection, and parallelization to power optimization, this book provides a comprehensive description of emerging multicore systems-on-chip (MCSoCs) hardware and software design. Highlighting both fundamentals and advanced software and hardware design, it can serve as a primary textbook for advanced courses in MCSoCs design and embedded systems. The first three chapters introduce MCSoCs architectures, present design challenges and conventional design methods, and describe in detail the main building blocks of MCSoCs. Chapters 4, 5, and 6 discuss fundamental and advanced on-chip interconnection network technologies for multi and many core SoCs, enabling readers to understand the microarchitectures for on-chip routers and network interfaces that are essential in the context of latency, area, and power constraints. With the rise of multicore and many-core systems, concurrency is becoming a major issue in the daily life of a programmer. Thus, compiler and software development tools are critical in helping programmers create high-performance software. Programmers should make sure that their parallelized program codes will not cause race condition, memory-access deadlocks, or other faults that may crash their entire systems. As such, Chapter 7 describes a novel parallelizing compiler design for high-performance computing. Chapter 8 provides a detailed investigation of power reduction techniques for MCSoCs at component and network levels. It discusses energy conservation in general hardware design, and also in embedded multicore system components, such as CPUs, disks, displays and memories. Lastly, Chapter 9 presents a real embedded MCSoCs system design targeted for health monitoring in the elderly.
Author: Bryon Moyer
Publisher: Newnes
ISBN: 0123914612
Category : Computers
Languages : en
Pages : 646
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Book Description
This Expert Guide gives you the techniques and technologies in embedded multicore to optimally design and implement your embedded system. Written by experts with a solutions focus, this encyclopedic reference gives you an indispensable aid to tackling the day-to-day problems when building and managing multicore embedded systems. Following an embedded system design path from start to finish, our team of experts takes you from architecture, through hardware implementation to software programming and debug. With this book you will learn: • What motivates multicore • The architectural options and tradeoffs; when to use what • How to deal with the unique hardware challenges that multicore presents • How to manage the software infrastructure in a multicore environment • How to write effective multicore programs • How to port legacy code into a multicore system and partition legacy software • How to optimize both the system and software • The particular challenges of debugging multicore hardware and software Examples demonstrating timeless implementation details Proven and practical techniques reflecting the authors’ expertise built from years of experience and key advice on tackling critical issues
Author: Arslan Munir
Publisher: John Wiley & Sons
ISBN: 1119086418
Category : Computers
Languages : en
Pages : 399
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Book Description
This book introduces the state-of-the-art in research in parallel and distributed embedded systems, which have been enabled by developments in silicon technology, micro-electro-mechanical systems (MEMS), wireless communications, computer networking, and digital electronics. These systems have diverse applications in domains including military and defense, medical, automotive, and unmanned autonomous vehicles. The emphasis of the book is on the modeling and optimization of emerging parallel and distributed embedded systems in relation to the three key design metrics of performance, power and dependability. Key features: Includes an embedded wireless sensor networks case study to help illustrate the modeling and optimization of distributed embedded systems. Provides an analysis of multi-core/many-core based embedded systems to explain the modeling and optimization of parallel embedded systems. Features an application metrics estimation model; Markov modeling for fault tolerance and analysis; and queueing theoretic modeling for performance evaluation. Discusses optimization approaches for distributed wireless sensor networks; high-performance and energy-efficient techniques at the architecture, middleware and software levels for parallel multicore-based embedded systems; and dynamic optimization methodologies. Highlights research challenges and future research directions. The book is primarily aimed at researchers in embedded systems; however, it will also serve as an invaluable reference to senior undergraduate and graduate students with an interest in embedded systems research.
Author: Ben Abadallah Abderazek
Publisher: Springer Science & Business Media
ISBN: 9491216333
Category : Computers
Languages : en
Pages : 196
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Book Description
Conventional on-chip communication design mostly use ad-hoc approaches that fail to meet the challenges posed by the next-generation MultiCore Systems on-chip (MCSoC) designs. These major challenges include wiring delay, predictability, diverse interconnection architectures, and power dissipation. A Network-on-Chip (NoC) paradigm is emerging as the solution for the problems of interconnecting dozens of cores into a single system on-chip. However, there are many problems associated with the design of such systems. These problems arise from non-scalable global wire delays, failure to achieve global synchronization, and difficulties associated with non-scalable bus-based functional interconnects. The book consists of three parts, with each part being subdivided into four chapters. The first part deals with design and methodology issues. The architectures used in conventional methods of MCSoCs design and custom multiprocessor architectures are not flexible enough to meet the requirements of different application domains and not scalable enough to meet different computation needs and different complexities of various applications. Several chapters of the first part will emphasize on the design techniques and methodologies. The second part covers the most critical part of MCSoCs design — the interconnections. One approach to addressing the design methodologies is to adopt the so-called reusability feature to boost design productivity. In the past years, the primitive design units evolved from transistors to gates, finite state machines, and processor cores. The network-on-chip paradigm offers this attractive property for the future and will be able to close the productivity gap. The last part of this book delves into MCSoCs validations and optimizations. A more qualitative approach of system validation is based on the use of formal techniques for hardware design. The main advantage of formal methods is the possibility to prove the validity of essential design requirements. As formal languages have a mathematical foundation, it is possible to formally extract and verify these desired properties of the complete abstract state space. Online testing techniques for identifying faults that can lead to system failure are also surveyed. Emphasis is given to analytical redundancy-based techniques that have been developed for fault detection and isolation in the automatic control area.
Author: Peter Marwedel
Publisher: Springer Science & Business Media
ISBN: 1461523230
Category : Computers
Languages : en
Pages : 298
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Book Description
Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation. In order to combine this growing system complexity with an increasingly short time-to-market, new system design technologies are emerging based on the paradigm of embedded programmable processors. This concept introduces modularity, flexibility and re-use in the electronic system design process. However, its success will critically depend on the availability of efficient and reliable CAD tools to design, programme and verify the functionality of embedded processors. Recently, new research efforts emerged on the edge between software compilation and hardware synthesis, to develop high-quality code generation tools for embedded processors. Code Generation for Embedded Systems provides a survey of these new developments. Although not limited to these targets, the main emphasis is on code generation for modern DSP processors. Important themes covered by the book include: the scope of general purpose versus application-specific processors, machine code quality for embedded applications, retargetability of the code generation process, machine description formalisms, and code generation methodologies. Code Generation for Embedded Systems is the essential introduction to this fast developing field of research for students, researchers, and practitioners alike.
