Author: Robert Stewart Lewis
Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
An Approach to Test Pattern Generation for Synchronous Sequential Circuits
Author: Robert Stewart Lewis
Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
Automatic Test Pattern Generation for Synchronous Sequential Circuits
Author: Marinus Hendrik Konijnenburg
Publisher:
ISBN: 9789090120966
Category :
Languages : en
Pages : 226
Book Description
Publisher:
ISBN: 9789090120966
Category :
Languages : en
Pages : 226
Book Description
Hierarchical Test Pattern Generation and Untestability Identification Techniques for Synchronous Sequential Circuits
Author: Anna Rannaste
Publisher:
ISBN: 9789949230419
Category :
Languages : en
Pages : 127
Book Description
Publisher:
ISBN: 9789949230419
Category :
Languages : en
Pages : 127
Book Description
Sequential Circuit Test Pattern Generation Using Empirical Partial Scan and Distributed Computation
Author: Kee Sup Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 386
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 386
Book Description
Stochastic Modeling in Fault Testing of Decomposable Sequential Circuits Through Computer Simulation
Author: Seong Yeon Choi
Publisher:
ISBN:
Category : Fault-tolerant computing
Languages : en
Pages : 240
Book Description
In this thesis, the detection of permanent faults in sequential circuits by random testing is analyzed utilizing the circuit partitioning approach together with a continuous parameter Markov model. Given a large decomposable sequential circuit, it is partitioned into several smaller partitions using either serial or parallel decomposition. For each partition with certain stuck faults specified, the original state table and its error version are derived from an analysis of the partition under fault-free and faulty conditions, respectively. Then by simulation of these two tables on a computer, the parameters of the desired Markov model are obtained. For a specified degree of confidence, it is easy to derive the parameters of the Markov model and to calculate the required lengths of random test patterns.
Publisher:
ISBN:
Category : Fault-tolerant computing
Languages : en
Pages : 240
Book Description
In this thesis, the detection of permanent faults in sequential circuits by random testing is analyzed utilizing the circuit partitioning approach together with a continuous parameter Markov model. Given a large decomposable sequential circuit, it is partitioned into several smaller partitions using either serial or parallel decomposition. For each partition with certain stuck faults specified, the original state table and its error version are derived from an analysis of the partition under fault-free and faulty conditions, respectively. Then by simulation of these two tables on a computer, the parameters of the desired Markov model are obtained. For a specified degree of confidence, it is easy to derive the parameters of the Markov model and to calculate the required lengths of random test patterns.
Incremental Test Pattern Generation for Sequential Circuits
Author: Bogdan Madzar
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 228
Book Description
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 228
Book Description
An Automatic Test Pattern Generation Technique for Sequential Circuits Using Scan Applications
Author: Venkat N. Koripalli
Publisher:
ISBN:
Category :
Languages : en
Pages : 74
Book Description
The increase in speed and the shrinking of technology has led to modern day ICs becoming more sensitive to timing related defects. These defects must be rectified to prevent hazards in the circuit. The timing related defects can be identified with At-Speed Testing using the path delay fault model. A subset of the total number of paths known as critical paths cannot be sequentially activated i.e. we cannot find two successive vectors that activate a fault along the path. The elimination of untestable paths helps us to save a lot of time. In this report a new method, called the Launch-on-Shift is used to determine the testability of critical paths. The method uses a vector pair in which the first vector is the scan in steady state vector and the second vector is the function of the first vector.
Publisher:
ISBN:
Category :
Languages : en
Pages : 74
Book Description
The increase in speed and the shrinking of technology has led to modern day ICs becoming more sensitive to timing related defects. These defects must be rectified to prevent hazards in the circuit. The timing related defects can be identified with At-Speed Testing using the path delay fault model. A subset of the total number of paths known as critical paths cannot be sequentially activated i.e. we cannot find two successive vectors that activate a fault along the path. The elimination of untestable paths helps us to save a lot of time. In this report a new method, called the Launch-on-Shift is used to determine the testability of critical paths. The method uses a vector pair in which the first vector is the scan in steady state vector and the second vector is the function of the first vector.
Automatic test pattern generation for hierarchical sequential circuits
Author: Heinrich Theodor Vierhaus
Publisher:
ISBN:
Category :
Languages : de
Pages : 19
Book Description
Publisher:
ISBN:
Category :
Languages : de
Pages : 19
Book Description
Performance of a Parallel Automatic Test Pattern Generation System for Sequential Circuits
Author: Jessica L. Handy
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
Test Pattern Generation for ILA Sequential Circuits
Author: YĆ¼ Feng
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 48
Book Description
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 48
Book Description