An Analog Decoder for Turbo-Structured Low-Density Parity-Check Codes PDF Download
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Author: Ali Reza Rabbani Abolfazli
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Languages : en
Pages :
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Author: Ali Reza Rabbani Abolfazli
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Languages : en
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Author: Saeed Sharifi Tehrani
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Languages : en
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Author: Sanjoy Basak
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Category :
Languages : en
Pages : 190
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The receiver side of many communication systems incorporates an error-correction decoder to achieve good bit-error rate (BER) performance. While good BER is a metric of reliable communication, high throughput and energy-efficiency are also desired. Low-density parity-check (LDPC) decoders are able to perform well in term of these metrics. In this thesis, the Modified Differential Decoding Binary Message Passing (MDD-BMP) algorithm of LDPC codes has been chosen to implement in mixed-signal domain. The goal of this research is to achieve energy-efficiency in LDPC decoding while maintaining high-throughput in an implemented design of reasonable effective area. The re-design of some digital parts of the LDPC decoder in analog domain is expected to offer energy-efficiency and high throughput. However, these benefits come at a cost of analog impairments, such as, different random mismatch between similar inverters arising from process variation during fabrication. The comparative contribution of these impairments on the BER performance of the decoder has been investigated. During the design of the decoder, an on-chip calibration scheme has been arranged and global routing of the tuning signals has been maintained to address these random mismatches. Furthermore, modulation of the decoding speed by off-chip tuning has been made possible. For the purpose of high-speed testing of the decoding process, enough on-chip memory has been placed to store 10 codewords and feed them to the decoder through a binary-weighted capacitor-based digital to analog converter. Design and placement of analog MUXes enable us to debug sensitive analog nodes inside the decoder from off-chip. Finally, the full process of the physical design of the decoder in TSMC 65nm has been almost fully automated in Cadence SKILL code. Over 100 simulations including parasitic capacitance of long wires in physical design yield an average decoding speed of approximately 2.04 ns in moderate speed mode, therefore, providing a high throughput of 134 Gb/s. Taking into account the average current drawn by the circuits during both the pre-charge phase and the decoding phase, the calculated average energy per bit consumed by the decoder is 1.267 pJ/bit.
Author: Juntan Zhang
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Category : Error-correcting codes (Information theory)
Languages : en
Pages : 288
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Author: Sunitha Kopparthi
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Languages : en
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Future technologies such as cognitive radio require flexible and reliable hardware architectures that can be easily configured and adapted to varying coding parameters. The objective of this work is to develop a flexible hardware encoder and decoder for low-density parity-check (LDPC) codes. The design methodologies used for the implementation of a LDPC encoder and decoder are flexible in terms of parity-check matrix, code rate and code length. All these designs are implemented on a programmable chip and tested. Encoder implementations of LDPC codes are optimized for area due to their high complexity. Such designs usually have relatively low data rate. Two new encoder designs are developed that achieve much higher data rates of up to 844 Mbps while requiring more area for implementation. Using structured LDPC codes decreases the encoding complexity and provides design flexibility. The architecture for an encoder is presented that adheres to the structured LDPC codes defined in the IEEE 802.16e standard. A single encoder design is also developed that accommodates different code lengths and code rates and does not require re-synthesis of the design in order to change the encoding parameters. The flexible encoder design for structured LDPC codes is also implemented on a custom chip. The maximum coded data rate of the structured encoder is up to 844 Mbps and for a given code rate its value is independent of the code length. An LDPC decoder is designed and its design methodology is generic. It is applicable to both structured and any randomly generated LDPC codes. The coded data rate of the decoder increases with the increase in the code length. The number of decoding iterations used for the decoding process plays an important role in determining the decoder performance and latency. This design validates the estimated codeword after every iteration and stops the decoding process when the correct codeword is estimated which saves power consumption. For a given parity-check matrix and signal-to-noise ratio, a procedure to find an optimum value of the maximum number of decoding iterations is presented that considers the affects of power, delay, and error performance.
Author: Kai Zhang
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Category :
Languages : en
Pages : 244
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Abstract: The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted to exploring efficient VLSI architectures for high-performance LDPC decoders and LDPC-like detectors in sparse inter-symbol interference (ISI) channels. The performance of an LDPC decoder is mainly evaluated by area efficiency, error-correcting capability, throughput and rate flexibility. With this work we investigate tradeoffs between the four performance aspects and develop several decoder architectures to improve one or several performance aspects while maintaining acceptable values for other aspects ... Layered decoding algorithm, which is popular in LDPC decoding, is also adopted in this paper. Simulation results show that the layered decoding doubles the convergence speed of the iterative belief propagation process. Exploring the special structure of the connections between the check nodes and the variable nodes on the factor graph, we propose an effective detector architecture for generic sparse ISI channels to facilitate the practical application of the proposed detection algorithm. The proposed architecture is also reconfigurable in order to switch flexible connections on the factor graph in the time-varying ISI channels.
Author: Chen Jinghu
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Category : Decoders (Electronics)
Languages : en
Pages : 234
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Author: Ahmed Refaey Ahmed Hussein
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Category : Coding theory
Languages : en
Pages : 0
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De nombreux systèmes de communication sans fil ont adopté les codes turbo et les codes convolutifs comme schéma de codes correcteurs d'erreurs vers l'avant (FEC) pour les données et les canaux généraux. Toutefois, certaines versions proposent les codes LDPC pour la correction d'erreurs en raison de la complexité de l'implémentation des décodeurs turbo et le succès de certains codes LDPC irréguliers dans la réalisation des mêmes performances que les codes turbo les dépassent dans certains cas avec une complexité de décodage plus faible. En fait, les nouvelles versions des standards de ces systèmes travaillent côte à côte dans des dispositifs réels avec les plus anciennes qui sont basées sur les codes turbo et les codes convolutifs. En effet, ces deux familles de codes offrent toutes deux d'excellentes performances en termes de taux d'erreur binaire (TEB). Par conséquent, il semble être une bonne idée d'essayer de les relier de manière à améliorer le transfert de technologie et l'hybridation entre les deux méthodes. Ainsi, la conception efficace de décodeurs universels des codes convolutifs, turbo, et LDPC est critique pour l'avenir de l'implémentation des systèmes sans fil. En outre, un décodeur efficace pour les codes turbo et codes convolutifs est obligatoire pour la mise en oeuvre de ces systèmes sans fil. Cela pourrait se faire par l'élaboration d'un algorithme de décodage unifié des codes convolutifs, turbo et LDPC par des simulations et des études analytiques suivies d'une phase de mise en oeuvre. Pour introduire ce décodeur universel, il existe deux approches, soit sur la base de l'algorithme du maximum a posteriori (MAP) ou l'algorithme de propagation de croyance (BP). D'une part, nous étudions une nouvelle approche pour décoder les codes convolutifs et les turbo codes au moyen du décodeur par propagation de croyances (BP) décodeur utilisé pour les codes de parité à faible densité (codes LDPC). En outre, nous introduisons un système de représentation général pour les codes convolutifs par des matrices de contrôle de parité. De plus, les matrices de contrôle de parité des codes turbo sont obtenus en traitant les codes turbo parallèles comme des codes convolutifs concaténés. En effet, l'algorithme BP fournit une méthodologie très efficace pour la conception générale des algorithmes de décodage itératif de faible complexité pour toutes les classes des codes convolutifs ainsi que les turbo-codes. Alors qu'une petite perte de performance est observée lors du décodage de codes turbo avec BP au lieu du MAP, cela est compensé par la complexité moindre de l'algorithme BP et les avantages inhérents à une architecture unifiée de décodage. En outre, ce travail exploite la représentation tail-biting de la matrice de contrôle de parité des codes convolutifs et des codes turbo, ce qui permet le décodage par un algorithme de propagation de croyance unifiée (BP) pour les nouveaux systèmes de communication sans fils tels que le WiMAX (Worldwide Interoperability for Microwave Access) et le LTE (Long Term Evolution). D'autre part, comme solution alternative, une recherche est effectuée sur la façon de produire un décodeur combiné de ces deux familles de codes basé sur l'algorithme MAP. Malheureusement, cette seconde solution nécessite beaucoup de calculs et de capacité de stockage pour sa mise en oeuvre. En outre, ses récurrences en avant et en arrière résultent en de longs délais de décodage. Entre temps, l'algorithme MAP est basé sur le treillis et la structure en treillis du code LDPC est suffisamment compliquée en raison de la matrice de contrôle de parité de grande taille. En conséquence, cette approche peut être difficile à mettre en oeuvre efficacement car elle nécessite beaucoup de calculs et une grande capacité de stockage. Enfin, pour prédire le seuil de convergence des codes turbo, nous avons appliqué la méthode de transfert d'information extrinsèque (EXIT) pour le décodeur correspondant en le traitant comme une concaténation de noeuds de variable et de contrôle.
Author: Jilei Hou
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Category :
Languages : en
Pages : 316
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Author: Giuseppe Gentile
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Category :
Languages : en
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