A Study on Electrical and Material Characteristics of Hafnium Oxide with Silicon Interface Passivation on III-V Substrate for Future Scaled CMOS Technology

A Study on Electrical and Material Characteristics of Hafnium Oxide with Silicon Interface Passivation on III-V Substrate for Future Scaled CMOS Technology PDF Author: Injo Ok
Publisher:
ISBN:
Category : Dielectrics
Languages : en
Pages : 246

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Book Description
The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO2 gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO2 (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x1010 eV−1cm−2), low gate leakage current, higher dielectric breakdown immunity (e"0MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO2 film. HfO2 based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility.

A Study on Electrical and Material Characteristics of Hafnium Oxide with Silicon Interface Passivation on III-V Substrate for Future Scaled CMOS Technology

A Study on Electrical and Material Characteristics of Hafnium Oxide with Silicon Interface Passivation on III-V Substrate for Future Scaled CMOS Technology PDF Author: Injo Ok
Publisher:
ISBN:
Category : Dielectrics
Languages : en
Pages : 246

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Book Description
The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO2 gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO2 (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x1010 eV−1cm−2), low gate leakage current, higher dielectric breakdown immunity (e"0MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO2 film. HfO2 based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility.

Fundamentals of III-V Semiconductor MOSFETs

Fundamentals of III-V Semiconductor MOSFETs PDF Author: Serge Oktyabrsky
Publisher: Springer Science & Business Media
ISBN: 1441915478
Category : Technology & Engineering
Languages : en
Pages : 451

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Book Description
Fundamentals of III-V Semiconductor MOSFETs presents the fundamentals and current status of research of compound semiconductor metal-oxide-semiconductor field-effect transistors (MOSFETs) that are envisioned as a future replacement of silicon in digital circuits. The material covered begins with a review of specific properties of III-V semiconductors and available technologies making them attractive to MOSFET technology, such as band-engineered heterostructures, effect of strain, nanoscale control during epitaxial growth. Due to the lack of thermodynamically stable native oxides on III-V's (such as SiO2 on Si), high-k oxides are the natural choice of dielectrics for III-V MOSFETs. The key challenge of the III-V MOSFET technology is a high-quality, thermodynamically stable gate dielectric that passivates the interface states, similar to SiO2 on Si. Several chapters give a detailed description of materials science and electronic behavior of various dielectrics and related interfaces, as well as physics of fabricated devices and MOSFET fabrication technologies. Topics also include recent progress and understanding of various materials systems; specific issues for electrical measurement of gate stacks and FETs with low and wide bandgap channels and high interface trap density; possible paths of integration of different semiconductor materials on Si platform.

Dissertation Abstracts International

Dissertation Abstracts International PDF Author:
Publisher:
ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 810

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Physics and Technology of High-k Gate Dielectrics 5

Physics and Technology of High-k Gate Dielectrics 5 PDF Author: Samares Kar
Publisher: The Electrochemical Society
ISBN: 1566775701
Category : Dielectrics
Languages : en
Pages : 676

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Book Description
This issue covers in detail all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, high dielectric constant materials, processing, metals for gate electrodes, interfaces, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.

Electrical and Material Characteristics of Hafnium-based Multi-metal High-k Gate Dielectrics for Future Scaled CMOS Technology

Electrical and Material Characteristics of Hafnium-based Multi-metal High-k Gate Dielectrics for Future Scaled CMOS Technology PDF Author: Se Jong Rhee
Publisher:
ISBN:
Category : Dielectrics
Languages : en
Pages :

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Atomic Layer Deposited Beryllium Oxide as a Gate Dielectric Or Interfacial Layer for Si and III-V MOS Devices

Atomic Layer Deposited Beryllium Oxide as a Gate Dielectric Or Interfacial Layer for Si and III-V MOS Devices PDF Author: Jung Hwan Yum
Publisher:
ISBN:
Category :
Languages : en
Pages : 226

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Book Description
The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO2 gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO2 (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x1010 eV−1cm−2), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO2 film. HfO2 based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility. High electron mobility in the III-V materials has attracted significant attention for a possible application as a channel material in metal/oxide/semiconductor (MOS) transistors. One of the main challenges is that III-V MOSFETs generally lack thermodynamically stable insulators of high electrical quality, which would passivate the interface states at the dielectric/substrate interface and unpin the Fermi level. To address this issue, various dielectric, such as Si/SiO2, Ge, SiGe, SiN and Al2O3, were considered as an interface passivation layer (IPL). Atomic Layer Deposited (ALD) Al2O3 has demonstrated superior IPL characteristics compared to the other candidates due to its high dielectric constant and interface quality. However, defect density in Al2O3 is still too high even as several cleaning methods such as NH4OH, (NH4)2S and F treatment have been developed, which limits the performance of III-V MOSFETs. In the first part of this study, theoretical approaches to understand the motivation and requirements as an high-k gate dielectric or interfacial layer, and properties of ALD beryllium oxide (BeO) for Si and III-V MOS devices have been investigated. The second part of this study focuses on the precursor synthesis and fundamental material characterization of ALD BeO thin film using physical, optical and electrical analysis. Film properties such as self-cleaning reaction and oxygen diffusion barrier will be presented. At the third part, depletion mode transistor and self-aligned MOSFETs using ALD BeO on Si and InP high mobility substrates have been investigated. And as for the final part of this study, the density functional theory of Be(CH3)2 precursor, electromagnetics, and thermodynamics were investigated to understand the reaction mechanism and self-cleaning reaction, and to evaluate the gate dielectrics such as Al2O3, BeO, SiO2, and HfO2.

Surface Passivation and Junction Engineering in Silicon

Surface Passivation and Junction Engineering in Silicon PDF Author: Gaurav Thareja
Publisher: Stanford University
ISBN:
Category :
Languages : en
Pages : 99

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Book Description
The planar silicon MOSFET is facing diminishing performance returns in improvement from device geometry scaling. Two alternative devices are being explored as possible solutions to this problem. The first contender is a multi-gate device (FINFET or surround gate) and the other is a MOSFET with high mobility channel material such as germanium, III-V or carbon. Ge has emerged as an important materials platform during recent years. With its high carrier mobility and the ability to detect and emit photons at telecommunications wavelengths, Ge is an attractive candidate for applications in both high performance electronics and optoelectronics. Moreover due to its compatibility with conventional CMOS fabrication, it can be processed using the standard manufacturing techniques that are currently used for silicon. However Ge does present a number of unique challenges that must be overcome, including issues of surface passivation, low n-type dopant solubility, and high dopant diffusivity. In this work, the unique properties of surface passivation enabled by radical oxidation are discussed. Some of the highlights are low temperature processing, substrate orientation independent growth rate of dielectric and low interface density. Subsequently, this radical oxidation is applied to 3D vertical gate all around (GAA) silicon MOSFET devices. Higher drive current, lower gate leakage and higher gate dielectric breakdown voltage are demonstrated for GAA devices using radical oxidation in comparison to thermal oxidation In the second part, radical oxidation is investigated for GeO2 growth as an interfacial layer in high-k / Ge gate stack. Using MOSCAP and n-MOSFET devices on Ge, low interface state density combined with drive current and electron mobility enhancement is demonstrated for Ge devices. In the third part, the source/drain junctions for Ge are studied. Ultra-shallow junctions using plasma immersion ion implantation are demonstrated. High n-type dopant activation in Ge using laser annealing is realized along with high performance diodes, significant reduction of contact resistance and integration in a MOSFET process flow.

Investigation of Electrical and Material Characteristics of High-k

Investigation of Electrical and Material Characteristics of High-k PDF Author: Yanzhen Wang
Publisher:
ISBN:
Category :
Languages : en
Pages : 248

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Book Description
In the past few decades, Si-based CMOS technology is approaching to its physical quantum limit by scaling down the gate length and gate oxide thickness to achieve higher drive current for low power and high speed application. High k/III-V stack provides an alternative solution because III-V based metal-oxide-semiconductor (MOS) devices have higher drive current due to the higher electron mobility than silicon. Also high k oxides lower the gate leakage current significantly due to larger thickness under the same equivalent oxide thickness (EOT) compared with SiO2 beyond the 22 nm node. The main obstacle for high k/III-V based MOSFETs is the lack of high quality, thermodynamically stable insulators that passivate the interface, which is also the main driving force in the research area of high k/III-V stack. One of the main focuses of this dissertation is developing a fabrication process flow to lower the interface trap density to enhance the performance of MOSFETs with high k oxides on III-V substrates. Also, an emerging memory device with SiO[subscript x] is also developed. This device can be electrically switched between a high-resistance state (HRS, or OFF-state) and a low-resistance state (LRS, or ON-state). Also it shows high potential for next generation nonvolatile memories due to its small cell area, fast write/erase time, low write voltage, good endurance and scalability. The other main focuses of this dissertation is studying the electroforming, set/reset voltages and passivation issue in this resistive random access memory (RRAM or ReRAM). The first part of this dissertation is about lowering the interface trap density of high k/III-V stack by using a thin layer of Al2O3 or LaAlO3. ALD Al2O3/HfO2 bi-layer gate oxide with different Al2O3 thickness (0, 5, 10Å) was deposited. Also ALD LaAlO3/HfO2 bi-layer gate oxide with different LaAlO3 thickness (0, 5, 10, 20, 30, 42Å) was deposited. The total EOT of the bi-layer was maintained at ~1.8nm. Also single La[subscript x]Al[subscript 1-X]O (X =0.25, 0.33, 0.5, 0.66, 0.75) gate dielectric with different La doping level was deposited (EOT=2.5±0.4nm). Device characteristics are compared by using different thickness of interfacial layer. The second part of this dissertation is about F incorporation into high k oxide by using SF6 plasma. The effect of SF6 plasma treatment of HfO2 on III-V substrates is demonstrated. Also effect of different plasma power and different treatment time of SF6 plasma is studied to optimize plasma conditions. High k bilayer (Al2O3/HfO2) is also used to further improve the device performance by better interface passivation with Al2O3. HfO2 gate oxide dielectric is also engineered using SF6 plasma treatment to incorporate more F. The third part is a study of III-V tunneling FET using In[subscript 0.7]Ga[subscript 0.3]As p-n junction. The device performance with different n doping concentration is compared. Higher n doping concentration will increase the drive current by reducing the tunneling width while too higher n doping concentration results in tunneling in the middle of p-n junction and significantly increase the subthreshold swing. The forth part is the electroforming, set/reset and passivation study of ReRAM device with SiO[subscript x]. Different methods to reduce the electroforming voltage are developed. Set/reset process is also studied and a possible model is proposed to explain the set/ reset process. A new device structure without sidewall edge is studied for passivation and application in air. The final part is the summary of Ph.D work and also suggestions for future work are discussed.

Atomic Layer Deposition of Hafnium Dioxide on Sulfur-Passivated Silicon-Germanium Surfaces

Atomic Layer Deposition of Hafnium Dioxide on Sulfur-Passivated Silicon-Germanium Surfaces PDF Author: Maximillian Samuel Clemons
Publisher:
ISBN:
Category :
Languages : en
Pages : 42

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Book Description
To integrate SiGe into future CMOS devices, it is essential to realize reliable strategies to deposit very thin high-k dielectrics on SiGe surfaces with a low density of interfacial defects. HfO2 was deposited by atomic layer deposition (ALD) using HfCl4 and H2O precursors. The quality of interfaces was varied by ex-situ surface treatment prior to ALD, including HF clean and HF clean followed by wet ammonium sulfide treatment. Electrical properties of the interfaces were examined by variable frequency capacitance-voltage (C-V) spectroscopy. Interfaces passivated by sulfur were found to have nearly 2x smaller density of interface traps than HF-treated interfaces, particularly near the edge of the valence band. The effect of Pd/Ti/TiN as a gettering gate electrode on the electrical characteristics of the interfaces were compared with Ni. By using Pd/Ti/TiN gate electrodes, lower equivalent oxide thicknesses (EOT) were achieved, but no significant improvement in the interface quality was observed.

JJAP

JJAP PDF Author:
Publisher:
ISBN:
Category : Physics
Languages : en
Pages : 1450

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Book Description