Author: B. D. Carroll
Publisher:
ISBN:
Category :
Languages : en
Pages : 25
Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
A Study of Fault Diagnosis of Sequential Logic Networks
On Fault Diagnosis
Author: Louis Gwo-Jiun Chu
Publisher:
ISBN:
Category : Electric network analysis
Languages : en
Pages : 334
Book Description
Publisher:
ISBN:
Category : Electric network analysis
Languages : en
Pages : 334
Book Description
Fault Diagnosis of Multiple Output Combinational Logic Networks
Author: Heramb Singh
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description
Sequential Decision Trees for Fault Diagnosis in Combinational Logic Networks
Author: Doctor Israel Koren
Publisher:
ISBN:
Category :
Languages : en
Pages : 30
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 30
Book Description
A Study of Digital Network Structure and Its Relation to Fault Diagnosis
Author: John Patrick Hayes
Publisher:
ISBN:
Category : Electric networks
Languages : en
Pages : 272
Book Description
A network model, is introduced for the study of fault diagnosis in digital logic networks. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network can be obtained. The use of this model greatly simplifies fault analysis and test generation. The structure of the classes of indistinguishable faults in normal NAND networks is studied. It is shown that for certain types of networks, the indistinguishability classes can be characterized in a very simple manner. The conditions under which masking can occur are examined. These conditions lead to efficient methods for generating multiple-fault detection test sets. Some general bounds for the number of tests required by a network are examined. It is proven that for a n-input fanout-free network, the cardinality of any minimal detection or location test set lies between 2(square root of n) and 2n. It is argued that a 2-level realization of a random n-variable function requires, on the average, 2 to the (n-1) power tests to detect all faults. It is shown that for certain classes of functions there exists multi-level realizations which require relatively few tests, and for which complete detection test sets can easily be generated. (Author).
Publisher:
ISBN:
Category : Electric networks
Languages : en
Pages : 272
Book Description
A network model, is introduced for the study of fault diagnosis in digital logic networks. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network can be obtained. The use of this model greatly simplifies fault analysis and test generation. The structure of the classes of indistinguishable faults in normal NAND networks is studied. It is shown that for certain types of networks, the indistinguishability classes can be characterized in a very simple manner. The conditions under which masking can occur are examined. These conditions lead to efficient methods for generating multiple-fault detection test sets. Some general bounds for the number of tests required by a network are examined. It is proven that for a n-input fanout-free network, the cardinality of any minimal detection or location test set lies between 2(square root of n) and 2n. It is argued that a 2-level realization of a random n-variable function requires, on the average, 2 to the (n-1) power tests to detect all faults. It is shown that for certain classes of functions there exists multi-level realizations which require relatively few tests, and for which complete detection test sets can easily be generated. (Author).
Optimising automatic fault detection and diagnostics for large sequential logic networks
Author: G. C. Jain
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
Fault Diagnosis in Combinational Logic Networks
Author: Robert B. Sieffert
Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
Research in Progress
Author:
Publisher:
ISBN:
Category : Military research
Languages : en
Pages : 494
Book Description
Publisher:
ISBN:
Category : Military research
Languages : en
Pages : 494
Book Description
Multiple Fault Diagnosis in Combinational Networks
Author: Charles Wei-Yuan Cha
Publisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Publisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Fault Diagnosis of Digital Systems
Author: Herbert Y. Chang
Publisher: Krieger Publishing Company
ISBN:
Category : Computers
Languages : en
Pages : 186
Book Description
Publisher: Krieger Publishing Company
ISBN:
Category : Computers
Languages : en
Pages : 186
Book Description